Determining the location of the ModelSim executable...

Using: c:/intelfpga_lite/16.1/modelsim_ase/win32aloem/

To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.

**** Generating the ModelSim Testbench ****

quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Part3 -c Part3 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Waveform.vwf.vt"

Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
    Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
    Info: Copyright (C) 2016  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel MegaCore Function License Agreement, or other 
    Info: applicable license agreement, including, without limitation, 
    Info: that your use is for the sole purpose of programming logic 
    Info: devices manufactured by Intel and sold by Intel or its 
    Info: authorized distributors.  Please refer to the applicable 
    Info: agreement for further details.
    Info: Processing started: Thu Mar 11 20:47:37 2021
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Part3 -c Part3 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Waveform.vwf.vt"
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Completed successfully. 

Completed successfully. 

**** Generating the functional simulation netlist ****

quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/" Part3 -c Part3

Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
    Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
    Info: Copyright (C) 2016  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel MegaCore Function License Agreement, or other 
    Info: applicable license agreement, including, without limitation, 
    Info: that your use is for the sole purpose of programming logic 
    Info: devices manufactured by Intel and sold by Intel or its 
    Info: authorized distributors.  Please refer to the applicable 
    Info: agreement for further details.
    Info: Processing started: Thu Mar 11 20:47:38 2021
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/" Part3 -c Part3
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file Part3.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 4641 megabytes
    Info: Processing ended: Thu Mar 11 20:47:38 2021
    Info: Elapsed time: 00:00:00
    Info: Total CPU time (on all processors): 00:00:01

Completed successfully. 

**** Generating the ModelSim .do script ****

C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.do generated.

Completed successfully. 

**** Running the ModelSim simulation ****

c:/intelfpga_lite/16.1/modelsim_ase/win32aloem//vsim -c -do Part3.do

Reading C:/intelFPGA_lite/16.1/modelsim_ase/tcl/vsim/pref.tcl

# 10.5b

# do Part3.do

# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:47:39 on Mar 11,2021
# vlog -work work Part3.vo 
# -- Compiling module Part3
# -- Compiling module hard_block
# 
# Top level modules:
# 	Part3
# End time: 20:47:39 on Mar 11,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:47:39 on Mar 11,2021
# vlog -work work Waveform.vwf.vt 
# -- Compiling module Part3_vlg_vec_tst
# 
# Top level modules:
# 	Part3_vlg_vec_tst
# End time: 20:47:39 on Mar 11,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Part3_vlg_vec_tst 
# Start time: 20:47:39 on Mar 11,2021
# Loading work.Part3_vlg_vec_tst
# Loading work.Part3
# Loading work.hard_block
# ** Warning: (vsim-3017) Part3.vo(460): [TFMPC] - Too few port connections. Expected 8, found 7.
#    Time: 0 ps  Iteration: 0  Instance: /Part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~  File: nofile
# ** Warning: (vsim-3722) Part3.vo(460): [TFMPC] - Missing connection for port 'clk_dft'.
# ** Warning: (vsim-3017) Part3.vo(483): [TFMPC] - Too few port connections. Expected 8, found 7.
#    Time: 0 ps  Iteration: 0  Instance: /Part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~  File: nofile
# ** Warning: (vsim-3722) Part3.vo(483): [TFMPC] - Missing connection for port 'clk_dft'.
# after#26
# ** Note: $finish    : Waveform.vwf.vt(45)
#    Time: 1 us  Iteration: 0  Instance: /Part3_vlg_vec_tst
# End time: 20:47:39 on Mar 11,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 4

Completed successfully. 

**** Converting ModelSim VCD to vector waveform ****

Reading C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/Waveform.vwf...

Reading C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3.msim.vcd...

Processing channel transitions... 

Writing the resulting VWF to C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Part3/simulation/qsim/Part3_20210311204740.sim.vwf

Finished VCD to VWF conversion.

Completed successfully. 

All completed.